Semiconductor integrated circuit designs and manufacturing techniques continue to evolve. Great progress has been made over the past generation in all phases of integrated circuit manufacturing so as to improve reliability of the finished products. Reliability of integrated circuits is of paramount importance to all concerned: the manufacturer, the OEM customer, and the end used. Indeed, in some "mission critical" applications, such as medicine or extra terrestrial applications, reliability of such circuits can be a matter of life and death. Even in more pedestrian applications, circuit failures lead to wasted time and expense, not to mention erosion of the manufacturer's reputation.
Although, in general, reliability of integrated circuits has become very high, the relentless push toward higher levels of integration, while maintaining high levels of reliability, presents an ongoing challenge. Part of the integrated circuit manufacturer's quest to improve reliability involves failure analysis--the analysis of failed parts in order to determine what caused the failure. Most manufacturers maintain failure analysis departments, staffed by engineers and other professionals who are skilled in this specialty. Failure analysis typically includes applying selected voltages to circuit inputs and examining selected output voltage levels, either through the use of a functional tester or a mechanical probing system. A mechanical probing system allows the FA technician to apply probes to establish electrical connections to selected locations within the circuitry on a failed chip. However, this work is difficult and time consuming. The technician must visually locate the point of interest on the failed chip under a microscope, among thousands or millions of transistors and perhaps four or five layers of metal, and then manually position a probe at that point. Only a handful of probes can be applied using manual systems due to mechanical space limitations. The limited number of probes available limits the types of failure testing that can be accomplished in this manner.
Automated probe systems and functional testers are known for testing ICs at wafer sort, i.e. before packaging. Typically, an entire silicon wafer with perhaps hundreds of integrated circuits formed on it is functionally tested before the wafer is cut into individual chips or dies for packaging. At this stage, the integrated circuits are tested, one at a time, using a probe machine. The probe machine handles the wafers and positions a "probe card" contacting the particular circuit under test. The probe card has a number of individual probes--typically several hundred in the context of large-scale integrated circuits arranged--for contacting corresponding bonding pads along the peripheral edges of the chip. The probe card provides electrical connection of the chip to an automatic tester machine which measures various I/O ac and dc properties, and otherwise "exercises" the chip to confirm functionality. "Bad" parts are rejected while good ones are packaged (and sometimes retested) and shipped to customers. Wafer sorting systems of the type just described are not used for failure analysis, however, or are used only in limited ways, because failure analysis often requires testing and measurements at internal locations on the die that are not connected to bonding pads.
This problem can be illustrated using embedded memory in an ASIC as an example. Recent advances in semiconductor technology allow the use of increasingly large blocks of memory, such as synchronous RAM or asynchronous RAM cores in ASIC. It is commonplace today for a "system-on-a-chip" to include several megabytes of embedded RAM. Consequently, wafer testing of the ASIC during manufacture must include automatic testing of embedded memories. However, testing of embedded memory blocks in ASIC is very challenging for several reasons. First, a large number of patterns are required for a comprehensive memory test; and the number of patterns grows exponentially with the increasing size of memory. Moreover, accessing memory to apply the test and then to observe the response is a major challenge when the memory is buried deep in the logic.
Four ways to test embedded memories are known: ASIC functional testing, direct I/O multiplexing, boundary scan, and built-in self-test (BIST). In ASIC functional testing, operation of the memory is tested through the functionality of the ASIC. Detailed knowledge of the ASIC is required and, in any event, functional testing of the ASIC is not likely to provide adequate detail for failure analysis in the embedded RAM. Direct I/O multiplexing requires that memory I/Os be brought out to the chip I/Os. Each memory input and output pin is multiplexed to a chip level pin so that patterns can be applied directly. This increases delay at the I/O, and imposes routing constraints, as well as increasing the chip area.
Boundary scanning serially connects the inputs and the outputs of the memory in a boundary scan chain and are provides access to them through a serial chip-level scan input and output pin. Boundary scan works reasonably well for small memories and especially if the design implements scan for the surrounding logic. This method, however, adds delay through the scan cell, increases the number of serial scan test cycles, increases the size of the tester scan memory, and again, is unlikely to provide adequate detail for failure analysis.
Finally, built-in self-test is useful as it provides 100% fault coverage in a reasonable test time. Moreover, software tools are known for automatically synthesizing BIST circuitry for compiled memories. However, BIST circuitry adds additional complexity and area to the chip, as described in more detail with reference to FIG. 1, below. Moreover, BIST may be adequate to provide a "good/bad" decision at wafer probe time, but again it does not provide detailed analysis of the failure mode. Accordingly, when an ASIC is presented for failure analysis, and embedded RAM is the suspect, the manual probing techniques described above are likely to be necessary, even if the chip includes one or more of the embedded memory testing techniques just described. The BIST and/or boundary scan circuitry may do no more than confirm that the embedded memory is bad. The failure analysis engineer must determine the specific cause of the failure, usually beginning by identifying the specific location in the memory array where the failure occurs--called bit mapping.